VLSI SYSTEM ON A CHIP DESIGN MODULE

  • Number systems

  • Logic gates

  • Boolean expressions

  • Introduction to registers and counter

  • Introduction to Embedded systems

  • Synchronous Finite State Machine Design

  • Data-path elements – Arithmetic Structures

  • Introduction to Programmable Platforms

  • Design Capture and Simulation

  • Practical Digital System Design Examples

  • Hardware Modeling Overview,

  • Verilog language concepts

  • Modules and Ports

  • Dataflow Modeling

  • Introduction to Test benches

  • Operators

  • Procedural Statements

  • Controlled Operation Statements

  • Coding for Finite State Machines

  • Coding For Synthesis

  • Tasks and Functions

  • Advanced Verilog Test benches

  • FPGA Architecture - Basic Components of FPGA (LUT, CLB, Switch Matrix, IOB), FPGA Architecture of different families: 7-series and UltraScale devices, Zynq.

  • FPGA Design Flow – Xilinx Vivado tool Flow, Reading Reports, Implementing IP cores, Debugging Using Vivado Analyzer.

  • Optimal FPGA Design – HDL Coding Techniques for FPGA, FPGA Design Techniques, Synthesis Techniques, Implementation Options.

  • Static Timing Analysis – Global Timing Constraints, Path specific timing constraints, Achieving Timing Closure, Introduction to Reset techniques, Clock Domain Crossing, Multiple Clock Domains.

  • Introduction to Verification and Verification Plan.

  • Verification Tools.

  • Stimulus and Response.

  • Introduction to Bus Functional Models.

  • Verification environment and its components.

  • SystemVerilog for Verification - SystemVerilog Event Ordering, Clocking block and Program block, OOP's Concept of SystemVerilog - Parameterized classes, Virtual interface, Constrained Randomization techniques, Functional Coverage (Coverage Driven Verification), SystemVerilog Assertions.

  • Introduction to UVM

  • UVM Classes

  • UVM Factory

  • Sequence Item, Sequencer, Virtual Sequences

  • Transaction Level Modeling

  • UVM Reporting Methods

  • Development of Reusable Verification Environment